RC 控制器驱动开发

/*
 * pci_host_bridge - 表示一个PCI主机桥
 * 是RC控制器在内核中的抽象
 */
struct pci_host_bridge {
    struct device dev;
    struct pci_bus *bus;           /* 根总线 */
    struct list_head windows;      /* 资源窗口 */
    void *sysdata;                 /* 平台私有数据 */
    
    /* 回调函数 */
    int (*map_irq)(const struct pci_dev *, u8, u8);
    void (*swizzle_irq)(struct pci_dev *, u8 *, u8 *);
};

/*
 * pci_ops - 配置空间访问操作
 * RC驱动必须实现这些操作
 */
struct pci_ops {
    void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
    int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
    int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
};

/*
 * ECAM配置空间映射
 * 地址计算：Base + (Bus << 20) + (Device << 15) + (Function << 12) + Offset
 */
static void __iomem *ecam_map_bus(struct pci_bus *bus, unsigned int devfn, int where)
{
    struct my_rc_data *data = bus->sysdata;
    void __iomem *base = data->ecam_base;
    unsigned int busn = bus->number;
    unsigned int dev = PCI_SLOT(devfn);
    unsigned int fn = PCI_FUNC(devfn);
    
    u32 offset = (busn << 20) | (dev << 15) | (fn << 12) | (where & ~3);
    
    return base + offset;
}

static int ecam_read(struct pci_bus *bus, unsigned int devfn, 
                     int where, int size, u32 *val)
{
    void __iomem *addr = ecam_map_bus(bus, devfn, where);
    
    if (!addr) {
        *val = ~0;
        return PCIBIOS_DEVICE_NOT_FOUND;
    }
    
    *val = readl(addr);
    
    /* 根据size调整返回值 */
    if (size == 1)
        *val = (*val >> ((where & 3) * 8)) & 0xff;
    else if (size == 2)
        *val = (*val >> ((where & 3) * 8)) & 0xffff;
    
    return PCIBIOS_SUCCESSFUL;
}

static struct pci_ops ecam_ops = {
    .map_bus = ecam_map_bus,
    .read = ecam_read,
    .write = ecam_write,  /* 类似实现 */
};

/*
 * RC驱动probe函数示例
 */
static int my_rc_probe(struct platform_device *pdev)
{
    struct device *dev = &pdev->dev;
    struct pci_host_bridge *bridge;
    struct resource *cfg_res, *io_res, *mem_res;
    struct my_rc_data *data;
    int ret;
    
    /* 1. 分配host bridge结构 */
    bridge = devm_pci_alloc_host_bridge(dev, sizeof(*data));
    if (!bridge)
        return -ENOMEM;
    
    data = pci_host_bridge_priv(bridge);
    
    /* 2. 获取资源（从设备树或ACPI） */
    cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
    data->ecam_base = devm_ioremap_resource(dev, cfg_res);
    if (IS_ERR(data->ecam_base))
        return PTR_ERR(data->ecam_base);
    
    /* 3. 初始化硬件 */
    ret = my_rc_hw_init(pdev, data);
    if (ret)
        return ret;
    
    /* 4. 设置配置空间操作 */
    bridge->ops = &ecam_ops;
    bridge->sysdata = data;
    
    /* 5. 解析设备树 ranges → 资源窗口（I/O / MEM / DMA，填入 bridge->windows） */
    ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, &bridge->windows, &bridge->dma_ranges);
    if (ret)
        return ret;

    /* 6. 扫描根总线并注册 host bridge（枚举 + 资源分配 + 驱动绑定的统一入口） */
    ret = pci_host_probe(bridge);
    if (ret)
        return ret;

    return 0;
}

static const struct of_device_id my_rc_of_match[] = {
    { .compatible = "vendor,pcie-rc", },
    { }
};

static struct platform_driver my_rc_driver = {
    .probe = my_rc_probe,
    .driver = {
        .name = "my-pcie-rc",
        .of_match_table = my_rc_of_match,
    },
};
builtin_platform_driver(my_rc_driver);

/* ARM平台设备树示例 */
pcie@40000000 {
    compatible = "vendor,pcie-rc";
    reg = <0x40000000 0x01000000>,    /* 配置空间 */
          <0x41000000 0x00100000>;    /* RC寄存器 */
    reg-names = "config", "ctrl";
    
    #address-cells = <3>;
    #size-cells = <2>;
    ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000>;
    
    bus-range = <0x00 0x0f>;   /* 16MB ECAM 窗口：1MB/总线 × 16 条总线（bus 0x00–0x0f）
                                  若需 256 条总线，config 空间需扩到 256MB（如 4KB/设备 × 8函数 × 32设备/总线） */
    
    interrupts = ,
                 ;
    interrupt-names = "intx", "msi";
    
    #interrupt-cells = <1>;
    interrupt-map-mask = <0 0 0 7>;
    interrupt-map = <0 0 0 1 &gic GIC_SPI 120 ...>;
    
    status = "okay";
};

/* 枚举主链路（简化） */
pci_host_probe(bridge)
  └─ pci_scan_root_bus_bridge(bridge)
       └─ pci_scan_child_bus(bus)          /* DFS 扫描 */
            └─ pci_scan_slot / pci_scan_single_device
                 ├─ pci_scan_device()      /* 读 Vendor ID 探测设备 */
                 ├─ pci_setup_device()     /* 读 Header、Class、BAR */
                 │    └─ pci_read_bases()  /* BAR sizing（write-all-1s） */
                 └─ pci_scan_bridge()      /* Type 1 桥 → 递归扫描二级总线 */
  └─ pci_bus_add_devices(bridge->bus)      /* 驱动绑定 */
       └─ device_attach() → bus->match() → driver->probe()

/* BAR sizing 的硬件语义（pci_read_bases() 背后的规则） */
u32 orig, sz;
pci_read_config_dword(dev, bar_pos, &orig);       /* 1. 保存原值 */
pci_write_config_dword(dev, bar_pos, ~0u);        /* 2. 写全 1 */
pci_read_config_dword(dev, bar_pos, &sz);         /* 3. 回读：实现位保留，地址位被清 */
pci_write_config_dword(dev, bar_pos, orig);       /* 4. 恢复原值 */

/* 5. 解码：低 4 位（MEM）/低 2 位（IO）是类型标志位，屏蔽后取反加一 */
sz &= (sz & PCI_BASE_ADDRESS_SPACE) ? 0xFFFFFFFC : 0xFFFFFFF0;
size = (~sz + 1);                                 /* 例如回读 0xFFF00000 → 1MB */